The present invention relates generally to non-volatile memory and in particular the present invention relates to synchronous flash memory.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. Computers typically contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special-type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of non-volatile memory that can be erased in blocks instead of one byte at a time. A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at high clock speeds. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. Some synchronous non-volatile memory devices have been provided that use SDRAM commands to allow for easy implementation in current SDRAM systems. These memory devices, however, are susceptible to restrictions and limitations of the SDRAM specific commands.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a synchronous non-volatile memory that can be initiated without using restricted SDRAM commands.
The above-mentioned problems with non-volatile synchronous memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a synchronous flash memory device comprises an array of non-volatile memory cells, and control circuit to initiate a command operation in response to a predefined sequence of externally provided ACTIVE and READ or ACTIVE and WRITE commands.
In another embodiment, a synchronous flash memory device comprises an array of non-volatile memory cells, and a command register to store command data used to control flash memory operations. The command register is coupled to receive the command data through memory address connections during an initiate command operation mode. The initiate command operation mode is initiated using a sequence of ACTIVE/WRITE commands where WRITE is defined as CAS# signal low, a RAS# signal high, and a WE# signal low.
A method of providing commands in a synchronous flash memory comprise initiating a command register load operation using a predefined combination of ACTIVE/WRITE commands, where WRITE is defined as a low column address strobe (CAS#) signal, a high row address strobe (RAS#) signal, and a low write enable (WE#) signal. Command data is loaded into the command register using address connections of the synchronous flash memory in response to the command register load operation.
A method of providing commands in a synchronous flash memory comprises initiating a command register load operation using a predefined combination of ACTlVE/WRITE commands, where WRITE is defined as a low column address strobe (CAS#) signal, a high row address strobe (RAS#) signal, and a low write enable (WE#) signal, and ACTIVE is defined as a high column address strobe (CAS#) signal, a low row address strobe (RAS#) signal, and a high write enable (WE#) signal. Command data is loaded into the command register using address connections of the synchronous flash memory in response to the command register load operation.